Tech symposium enabled future engineers to share their thoughts on RISC-V ecosystem and understand the benefits of RISC-V
SiFive and Open-Silicon hosted a symposium for students and academicians to learn more about the open RISC-V instruction set architecture. Open-Silicon, a semiconductor solutions enterprise that is now part of SiFive, concluded their six-city RISC-V tech symposium tour in New Delhi on August 31st, 2018. The relay of symposiums started in Hyderabad and was also conducted in Bangalore, Chennai, Pune and Kolkata.
Academia an important part of the designer community
Along with industry experts, the tech symposium in New Delhi enabled students and future engineers to share their thoughts on the RISC-V ecosystem and understand the benefits of RISC-V. The open instruction set architecture(ISA) can act as an enabler to develop indigenous processors for businesses, control and security at the national government. It also helped to develop the current research being conducted at Indian educational institutes and research organisations.
The esteemed speakers used the platform to discuss the nuances of hardware designing and designing complex RISC -V SoCs. The six-city tour saw more than 1250 students, engineers, researchers and industry experts who were gathered and shared the platform with the esteemed speakers.
The event was attended by academic leaders and dignitaries such as Naresh Rana, Manager of Business Development at Western Digital, Smruti Ranjan Sarangi, Associate Professor in CSE at IIT Delhi, Kunal Ghosh, Director & Co-Founder and Anagha Ghosh, Business Head and Co-Founder of VSD. The SiFive team was represented by Swamy Irrinki, Sr. Director of Marketing, Dr Shafy Eltoukhy, SVP of Operations and GM of SoC Division, and also Huzefa Cutlerywala, MD of Open-Silicon India.
Announcement of ‘Design Contest’ in India
During the tour, SiFive also announced first of its kind ‘Design Contest’ in India. This contest aims to enable some of the underutilised ideas from Indian academic institutions, students, research groups, non-profits to individuals. SiFive will collaborate with the best ideas and provide the winners’ access to custom CPU IP, design support and help in delivering the working samples for the chip. The contest will run from August 21st to November 30th, 2018.
Huzefa Cutlerywala said, “Academic institutions and academicians will play a vital role in imparting the knowledge of these practically advanced design architectures to create more innovators. Universities should be the place where students should learn how to learn.”
The benefits of RISC-V
RISC-V is an open instruction set architecture (ISA) that allows chip designers to create, customise and manufacture their own chips and software using the ISA freely. Despite being a new ISA, the RISC-V platform provides a large selection of open-sourced CPU designs, multiple open source OS support like Linux, FreeBSD and NetBSD and an array of software tools as well.
Apart from the limited and clean instruction set provided by default, you can create your own instructions and choose to keep them private or public as you desire, provided due permissions are granted by RISC-V members.
Shafy Eltoukhy said, “The fact that this open architecture has the capacity to bring custom silicon to all inventors and makers will benefit the entire semiconductor ecosystem.” The RISC-V community is expanding with big global names like Google, NVidia, Microsemi, Western Digital among many others becoming members. Indian academic and research organisations like IIT-Madras and CDAC are also actively promoting RISC-V among the designer community.